Semiconductor memories are composed of large arrays of individual cells. Each cell stores a 1 or 0 bit of data as an electrical high or low voltage state. Conventionally 8 bits may compose a byte of data and at least 16 bits may compose a word. In each memory operation cycle, at least one byte is typically written into or read from the array. Cells are arranged at the crossings of vertical data, or bit-lines, and horizontal word-lines or address lines. The word-lines enable reading or writing operation. A read or write cycle occurs when a word-line, as well as a pair of bit-lines, are activated. The cell accessed at the intersection of the word-line and the bit-lines will either receive written data from the bit-lines, or will deliver written data to the bit-lines. Cells can be accessed in random order. A cell may also be accessed directly based on its location in the memory circuit.
A memory cell is composed of an electronic circuit, typically including transistors. A Static Random Access Memory (SRAM) memory cell is conventionally composed of a plurality of metal-oxide-semiconductor field-effect-transistors (MOSFETs). The most common type of SRAM is composed of six-transistor (6T) cells, each of which includes two P-type MOSFETs (PMOSFETs) and four N-type MOSFETs (NMOSFETs). A cell is arranged with two inverters that are accessed from two complementary bit-lines through two access transistors controlled by a word-line. Such structures have low power consumption and provide immunity to electronic noise.
FIG. 1 illustrates a conventional six-transistor SRAM cell 100. Specifically, FIG. 1 illustrates a six-transistor SRAM cell 100 with two additional resistors 102 and 104. Pull-up transistor PU-1 and pull-down transistor PD-1 form inverter INV-1. Similarly, pull-up transistor PU-2 and pull-down transistor PD-2 form inverter INV-2. Each of these resistors is placed between one inverter output node and the gates of the opposite inverter. From Node-2, a resistor 102 is in series with the parallel combination of the gate-to-substrate capacitance of a pull-up transistor PU-1 and of a pull-down transistor PD-1. From Node-1, a resistor 104 is in series with the parallel combination of the gate-to-substrate capacitance of a pull-up transistor PU-2 and of a pull-down transistor PD-2. Node-2 is also connected, through a pass-gate transistor PG-2, to bit-line bar BLB. Node-1 is also connected, through a pass-gate transistor PG-1 to bit-line BL. Pass-gate transistors PG-1 and PG-2 are switched by the word-line WL.
To avoid memory failure, each memory cell is configured to have a redundant memory arrangement nearby. Typically, the redundancy is in the form of a memory segment having several rows and columns of memory cells. In some embodiments, a row or column of memory cells is typically accompanied by a row or column of redundant memory cells. Thus, when a memory cell fails, a segment containing the defective memory cell is replaced with a redundant memory segment. The redundant memory segment are positioned near the applicable memory cells to male replacement easily accessible. In the event of a memory cell failure, the datum is directed to a corresponding redundant cell.
As memory systems continuously increase in size and complexity, the number of redundant memory segments also increases to accommodate a larger number of potentially defective cells. Redundant cells are typically allocated to a region of the memory circuit and a redundant memory segment in the closest proximity to the defective cell may be selected as a replacement. In certain designs, the redundant memory segments are added to the end of the region where the memory cells are housed. In the event of a memory cell failure, the information is directed to the redundant memory segment at the end of the memory region to replace the entire segment containing the defective cell.
However, as more technologies that utilize semiconductor memories require a smaller footprint and a higher mobility, space saving in semiconductor memory designs becomes increasingly important. In particular, in order to continually achieve size and performance advantages, cell geometries must continually shrink. Because of the one-to-one relationship between memory cells and their redundant regions, a larger memory size has been accompanied by a larger redundant region.